Highlights
- 2GHz 64-bit octo substance ARM® Cortex™ A53 CPU
- 750 MHz ARM Mali™-820MP3 GPU processor
- HW UHD H.265/VP9 60fps 10-bit video decoder as well as depression latency 1080 60fps video encoder
- Dolby Vision, HLG as well as HDR10 processing
- TrustZone based safety for DRM video streaming
- WIFI, BT, USB, SD, Ethernet, Analog Audio as well as TS peripheral ports
- Power administration auxiliary processor
S912 is an advanced application processor designed for high performance 4k OTT/IP Set Top Box (STB) as well as gaming box applications. It integrates a powerful CPU/GPU subsystem, a secured 4K video CODEC engine as well as a best-in-class HDR picture processing pipeline amongst all major peripherals to shape the ultimate depression ability multimedia AP. The primary organization CPU is an octa-core ARM Cortex-A53 CPU grouped into ii CPU clusters amongst large unified L2 cache. Each cluster, which consists of 4 Cortex-A53 cores amongst L1 instruction/data cache for each core, is controlled yesteryear DVFS software as well as tin forcefulness out last independently clocked upwards to 2GHz. In addition, the Cortex-A53 cores include the NEON SIMD co-processor as well as I/D-cache to ameliorate the overall organization performance.
The graphic subsystem consists of ii graphic engines as well as a flexible video/graphic output pipeline. The ARM Mali-T820MP3 GPU three shader engines, amongst 1 Arithmetic Unit (ALU ), 1 Load/Store Pipeline as well as 1 Texture Pipeline contained inwards each shader, handles all the OpenGL® ES 3.1/2.0/1.1, DirectX®11 FL9_3, OpenCL™ 1.1/1.2 sum profile as well as Android™ RenderScript; spell the 2.5D graphics processor handles additional scaling, alpha, rotation as well as color infinite conversion operations. Together, the CPU as well as GPU grip all operating system, networking, user-interface as well as gaming related tasks. The video output pipeline includes advanced HDR10, HLG as well as Dolby Vision HDR processing, REC709/BT2020 processing, motion adaptive border enhancing de-interlacing, flexible programmable scalar, as well as many painting demo enhancement filters earlier passing the enhanced picture to the video output ports.
Amlogic Video Engine (AVE-10) offloads the Cortex-A53 CPUs from all video CODEC processing. It includes dedicated hardware video decoder as well as encoder. AVE-10 is capable of decoding 4K2K resolution video at 60fps inside Trusted Video Path (TVP) for secured DRM applications. It supports all major video formats including MVC, MPEG-1/2/4, VC-1/WMV, AVS, AVS+, RealVideo, MJPEG streams, H.264, H265-10, VP9-10 as well as also JPEG. The independent encoder tin forcefulness out concurrently encode inwards JPEG, as well as H.264 upwards to 1080p at 60fps.
S912 integrates all touchstone audio/video input/output interfaces including a HDMI2.0a transmitter amongst 3D, HDR, CEC as well as HDCP 2.2 support, stereo well DAC outputs, a CVBS output, PCM, I2S as well as SPDIF digital well input/output interfaces, stereo PDM digital MIC inputs as well as DVP photographic television receiver camera interface. S912 also integrates a educate of functional blocks for digital TV broadcasting streams. The built-in ii demux tin forcefulness out procedure the TV streams from the series as well as parallel carry current input interface, which tin forcefulness out connect to external tuner/demodulator as well as CI+ module. An ISO7816 smart bill of fare interface as well as a crypto-processor are built inwards to help treatment encrypted traffic as well as media streams.
The processor has rich advanced network as well as peripheral interfaces, including a Gigabits Ethernet MAC amongst RGMII interface, 10/100M Ethernet PHY, triple USB 2.0 high-speed ports (one OTG as well as ii HOSTs) as well as multiple SDIO/SD bill of fare controllers, UART, I2C, highspeed SPI as well as PWMs. Standard evolution surroundings utilizing GNU/GCC Android tool chain is supported.
CPU Sub-system
- Octa substance ARM Cortex-A53 CPU upwards to 2GHz (DVFS)
- Two CPU clusters amongst 4 CPU cores for each, large cluster optimized for high-performance as well as picayune cluster optimized for depression power
- ARMv8-A architecture amongst Neon as well as Crypto extensions
- 8-stage in-order sum dual number pipeline
- Unified organization L2 cache
- Advanced TrustZone safety system
- Application based traffic optimization using internal QoS-based switching fabrics
3D Graphics Processing Unit
- ARM Mali-T820MP3 GPU upwards to 750MHz (DVFS)
- Built-in Memory Management Unit (MMU) as well as L2 cache
- 2250Mpix/sec as well as 350Mtri/sec
- OpenGL® ES 3.1/2.0/1.1, DirectX®11 FL9_3, OpenCL™ 1.1/1.2 sum profile as well as Android™ RenderScript support
2.5D Graphics Processor
- Fast bitblt engine amongst dual inputs as well as unmarried output
- Programmable raster operations (ROP)
- Programmable polyphase scaling filter
- Supports multiple video formats 4:2:0, 4:2:2 as well as 4:4:4 as well as multiple pixel formats (8/16/24/32 bits graphics layer)
- Fast color infinite conversion
- Advanced anti-flickering filter
Crypto Engine
- AES/AES-XTS block nix amongst 128/192/256 bits keys, touchstone sixteen bytes block size as well as streaming ECB, CBC as well as CTR modes
- DES/TDES block nix amongst ECB as well as CBC modes supporting 64 bits primal for DES as well as 192 bits primal for 3DES
- Hardware crypto key-ladder functioning as well as DVB-CSA for carry current encryption
- Built-in hardware True Random Number Generator (TRNG), CRC as well as SHA-1/SHA-2/HMAC SHA engine
Video/Picture CODEC
- Amlogic Video Engine (AVE) amongst dedicated hardware decoders as well as encoders
- Supports multiple “secured” video decoding sessions as well as simultaneous decoding as well as encoding
Video/Picture Decoding
- VP9-10 Profile-2 upwards to 4Kx2K@60fps
- H.265 HEVC MP-10@L5.1 upwards to 4Kx2K@60fps
- H.264 AVC HP@L5.1 upwards to 4Kx2K@30fps
- H.264 MVC upwards to 1080P @60fps
- MPEG-4 ASP@L5 upwards to 1080P@60fps (ISO-14496)
- WMV/VC-1 SP/MP/AP upwards to 1080P@60fps
- AVS-P16(AVS+) /AVS-P2 JiZhun Profile upwards to 1080P@60fps
- MPEG-2 MP/HL upwards to 1080P@60fps (ISO-13818)
- MPEG-1 MP/HL Up to 1080P@60fps (ISO-11172)
- RealVideo 8/9/10 upwards to 1080P@60fps
- WebM upwards to VGA
- Multiple linguistic communication as well as multiple format sub-title video support
- MJPEG as well as JPEG unlimited pixel resolution decoding (ISO/IEC-10918)
- Supports JPEG thumbnail, scaling, rotation as well as transition effects
- Supports *.mkv,*.wmv,*.mpg, *.mpeg, *.dat, *.avi, *.mov, *.iso,*.mp4, *.rm as well as *.jpg file formats
Video/Picture Encoding
- Independent JPEG as well as H.264 encoder amongst configurable performance/bit-rate
- JPEG picture encoding
- H.264 video encoding upwards to 1080P@60fps amongst depression latency
Video Post-Processing Engine
- Supports Dolby Vision, HDR10 as well as HLG HDR processing
- Motion adaptive 3D dissonance reduction filter
- Advanced motion adaptive border enhancing de-interlacing engine
- 3:2 pull-down support
- Programmable poly-phase scalar for both horizontal as well as vertical dimension for zoom as well as windowing
- Programmable color administration filter (to heighten blue, green, red, facial expression upwards as well as other colors)
- Dynamic Non-Linear Luma filter
- Deblocking filters
- Programmable color matrix pipeline
- Video mixer: 2 video planes as well as 2 graphics planes per video output
Video Output
- Built-in HDMI 2.0a transmitter including both controller as well as PHY with
HDR, CEC as well as HDCP 2,2, 4Kx2K@60 max resolution output
- CVBS 480i/576i touchstone Definition output
- RGB888 TTL interface amongst TCON upwards to 1920x1080 resolution
- Supports all touchstone SD/HD/FHD video output formats: 480i/p, 576i/p, 720p, 1080i/p as well as 4Kx2K
Camera Interface
- ITU 601/656 parallel video input amongst down-scalar
- Supports photographic television receiver camera input every bit YUV422, RGB565,16bit RGB or JPEG
Audio Decoder as well as Input/Output
- Supports MP3, AAC, WMA, RM, FLAC, Ogg as well as programmable amongst 7.1/5.1 down-mixing
- I2S well interface supporting 8-channel (7.1) input as well as output
- Built-in series digital well SPDIF/IEC958 output as well as PCM input/output
- Stereo digital microphone PDM input
- Built-in stereo well DAC
- Supports concurrent dual well stereo channel output amongst combination of analog+PCM or I2S+PCM
Memory as well as Storage Interface
- 16/32-bit SDRAM retentiveness interface running upwards to DDR2400
- Supports upwards to 2GB DDR3/4, DDR3L, LPDDR2/3 amongst dual ranks
- Supports SLC/MLC/TLC NAND Flash amongst 60-bit ECC, compatible to Toshiba toggle agency inwards add-on to ONFI 2.2
- SDSC/SDHC/SDXC bill of fare as well as SDIO interface amongst 1-bit as well as 4-bit information charabanc width supporting spec version 2.x/3.x/4.x DS/HS modes upwards to UHS-I SDR104
- eMMC as well as MMC bill of fare interface amongst 1/4/8-bit information charabanc width fully supporting spec version 5.0 HS400
- Supports series 1, 2 or 4-bit NOR Flash via SPI interface
- Built-in 4k bits One-Time-Programming retentiveness for primal storage
Network
- Integrated IEEE 802.3 10/100/1000M Gigabit Ethernet MAC controller with RGMII interface
- Integrated 10/100M PHY interface
- Supports Energy Efficiency Ethernet (EEE) mode
- Optional 50MHz as well as 125MHz clock output to external Ethernet PHY
- WiFi/IEEE802.11 & Bluetooth supporting via SDIO/USB/UART/PCM
- Network interface optimized for mixed WIFI as well as BT traffic
Digital Television Interface
- Transport current (TS) input interface amongst built-in demux processor for connecting to external digital TV tuner/demodulator as well as 1 output TS interface
- Built-in PWM, I2C as well as SPI interfaces to command tuner as well as demodulator
- Integrated CI+ port as well as ISO 7816 smart bill of fare controller
Integrated I/O Controllers as well as Interfaces
- Triple USB 2.0 high-speed USB I/O, ii USB Hosts as well as 1 USB OTG
- Multiple UART, I2C as well as SPI interface amongst slave select
- Multiple PWMs
- Programmable IR remote input/output controllers
- Built-in 10bit SAR ADC amongst 2 input channels
- Influenza A virus subtype H5N1 educate of General Purpose IOs amongst built-in clit upwards as well as clit down
System, Peripherals as well as Misc. Interfaces
- Integrated full general purpose timers, counters, DMA controllers
- 24 MHz crystal input
- Embedded debug interface using ICE/JTAG
Power Management
- Multiple external ability domains controlled yesteryear PMIC
- Multiple internal ability domains controlled yesteryear software
- Multiple slumber modes for CPU, system, DRAM, etc.
- Multiple internal PLLs for DVFS operation
- Multi-voltage I/O blueprint for 1.8V as well as 3.3V
- Power administration auxiliary processor inwards a dedicated always-on (AO) ability domain that tin forcefulness out communicate amongst an external PMIC
Security
- Trustzone based Trusted Execution Environment (TEE)
- Secured boot, encrypted OTP, encrypted DRAM amongst retentiveness integrity checker, hardware primal ladder as well as internal command buses as well as storage
- Protected retentiveness regions as well as electrical debate information partition
- Hardware based Trusted Video Path (TVP) , video watermarking as well as secured contents (needs SecureOS software)
- Secured IO as well as secured clock
Package
- LFBGA, 15mmx15mm, 0.65 ball pitch, RoHS compliant
- 2GHz 64-bit octo substance ARM® Cortex™ A53 CPU
- 750 MHz ARM Mali™-820MP3 GPU processor
- HW UHD H.265/VP9 60fps 10-bit video decoder as well as depression latency 1080 60fps video encoder
- Dolby Vision, HLG as well as HDR10 processing
- TrustZone based safety for DRM video streaming
- WIFI, BT, USB, SD, Ethernet, Analog Audio as well as TS peripheral ports
- Power administration auxiliary processor
S912 is an advanced application processor designed for high performance 4k OTT/IP Set Top Box (STB) as well as gaming box applications. It integrates a powerful CPU/GPU subsystem, a secured 4K video CODEC engine as well as a best-in-class HDR picture processing pipeline amongst all major peripherals to shape the ultimate depression ability multimedia AP. The primary organization CPU is an octa-core ARM Cortex-A53 CPU grouped into ii CPU clusters amongst large unified L2 cache. Each cluster, which consists of 4 Cortex-A53 cores amongst L1 instruction/data cache for each core, is controlled yesteryear DVFS software as well as tin forcefulness out last independently clocked upwards to 2GHz. In addition, the Cortex-A53 cores include the NEON SIMD co-processor as well as I/D-cache to ameliorate the overall organization performance.
The graphic subsystem consists of ii graphic engines as well as a flexible video/graphic output pipeline. The ARM Mali-T820MP3 GPU three shader engines, amongst 1 Arithmetic Unit (ALU ), 1 Load/Store Pipeline as well as 1 Texture Pipeline contained inwards each shader, handles all the OpenGL® ES 3.1/2.0/1.1, DirectX®11 FL9_3, OpenCL™ 1.1/1.2 sum profile as well as Android™ RenderScript; spell the 2.5D graphics processor handles additional scaling, alpha, rotation as well as color infinite conversion operations. Together, the CPU as well as GPU grip all operating system, networking, user-interface as well as gaming related tasks. The video output pipeline includes advanced HDR10, HLG as well as Dolby Vision HDR processing, REC709/BT2020 processing, motion adaptive border enhancing de-interlacing, flexible programmable scalar, as well as many painting demo enhancement filters earlier passing the enhanced picture to the video output ports.
Amlogic Video Engine (AVE-10) offloads the Cortex-A53 CPUs from all video CODEC processing. It includes dedicated hardware video decoder as well as encoder. AVE-10 is capable of decoding 4K2K resolution video at 60fps inside Trusted Video Path (TVP) for secured DRM applications. It supports all major video formats including MVC, MPEG-1/2/4, VC-1/WMV, AVS, AVS+, RealVideo, MJPEG streams, H.264, H265-10, VP9-10 as well as also JPEG. The independent encoder tin forcefulness out concurrently encode inwards JPEG, as well as H.264 upwards to 1080p at 60fps.
S912 integrates all touchstone audio/video input/output interfaces including a HDMI2.0a transmitter amongst 3D, HDR, CEC as well as HDCP 2.2 support, stereo well DAC outputs, a CVBS output, PCM, I2S as well as SPDIF digital well input/output interfaces, stereo PDM digital MIC inputs as well as DVP photographic television receiver camera interface. S912 also integrates a educate of functional blocks for digital TV broadcasting streams. The built-in ii demux tin forcefulness out procedure the TV streams from the series as well as parallel carry current input interface, which tin forcefulness out connect to external tuner/demodulator as well as CI+ module. An ISO7816 smart bill of fare interface as well as a crypto-processor are built inwards to help treatment encrypted traffic as well as media streams.
The processor has rich advanced network as well as peripheral interfaces, including a Gigabits Ethernet MAC amongst RGMII interface, 10/100M Ethernet PHY, triple USB 2.0 high-speed ports (one OTG as well as ii HOSTs) as well as multiple SDIO/SD bill of fare controllers, UART, I2C, highspeed SPI as well as PWMs. Standard evolution surroundings utilizing GNU/GCC Android tool chain is supported.
CPU Sub-system
- Octa substance ARM Cortex-A53 CPU upwards to 2GHz (DVFS)
- Two CPU clusters amongst 4 CPU cores for each, large cluster optimized for high-performance as well as picayune cluster optimized for depression power
- ARMv8-A architecture amongst Neon as well as Crypto extensions
- 8-stage in-order sum dual number pipeline
- Unified organization L2 cache
- Advanced TrustZone safety system
- Application based traffic optimization using internal QoS-based switching fabrics
3D Graphics Processing Unit
- ARM Mali-T820MP3 GPU upwards to 750MHz (DVFS)
- Built-in Memory Management Unit (MMU) as well as L2 cache
- 2250Mpix/sec as well as 350Mtri/sec
- OpenGL® ES 3.1/2.0/1.1, DirectX®11 FL9_3, OpenCL™ 1.1/1.2 sum profile as well as Android™ RenderScript support
2.5D Graphics Processor
- Fast bitblt engine amongst dual inputs as well as unmarried output
- Programmable raster operations (ROP)
- Programmable polyphase scaling filter
- Supports multiple video formats 4:2:0, 4:2:2 as well as 4:4:4 as well as multiple pixel formats (8/16/24/32 bits graphics layer)
- Fast color infinite conversion
- Advanced anti-flickering filter
Crypto Engine
- AES/AES-XTS block nix amongst 128/192/256 bits keys, touchstone sixteen bytes block size as well as streaming ECB, CBC as well as CTR modes
- DES/TDES block nix amongst ECB as well as CBC modes supporting 64 bits primal for DES as well as 192 bits primal for 3DES
- Hardware crypto key-ladder functioning as well as DVB-CSA for carry current encryption
- Built-in hardware True Random Number Generator (TRNG), CRC as well as SHA-1/SHA-2/HMAC SHA engine
Video/Picture CODEC
- Amlogic Video Engine (AVE) amongst dedicated hardware decoders as well as encoders
- Supports multiple “secured” video decoding sessions as well as simultaneous decoding as well as encoding
Video/Picture Decoding
- VP9-10 Profile-2 upwards to 4Kx2K@60fps
- H.265 HEVC MP-10@L5.1 upwards to 4Kx2K@60fps
- H.264 AVC HP@L5.1 upwards to 4Kx2K@30fps
- H.264 MVC upwards to 1080P @60fps
- MPEG-4 ASP@L5 upwards to 1080P@60fps (ISO-14496)
- WMV/VC-1 SP/MP/AP upwards to 1080P@60fps
- AVS-P16(AVS+) /AVS-P2 JiZhun Profile upwards to 1080P@60fps
- MPEG-2 MP/HL upwards to 1080P@60fps (ISO-13818)
- MPEG-1 MP/HL Up to 1080P@60fps (ISO-11172)
- RealVideo 8/9/10 upwards to 1080P@60fps
- WebM upwards to VGA
- Multiple linguistic communication as well as multiple format sub-title video support
- MJPEG as well as JPEG unlimited pixel resolution decoding (ISO/IEC-10918)
- Supports JPEG thumbnail, scaling, rotation as well as transition effects
- Supports *.mkv,*.wmv,*.mpg, *.mpeg, *.dat, *.avi, *.mov, *.iso,*.mp4, *.rm as well as *.jpg file formats
Video/Picture Encoding
- Independent JPEG as well as H.264 encoder amongst configurable performance/bit-rate
- JPEG picture encoding
- H.264 video encoding upwards to 1080P@60fps amongst depression latency
Video Post-Processing Engine
- Supports Dolby Vision, HDR10 as well as HLG HDR processing
- Motion adaptive 3D dissonance reduction filter
- Advanced motion adaptive border enhancing de-interlacing engine
- 3:2 pull-down support
- Programmable poly-phase scalar for both horizontal as well as vertical dimension for zoom as well as windowing
- Programmable color administration filter (to heighten blue, green, red, facial expression upwards as well as other colors)
- Dynamic Non-Linear Luma filter
- Deblocking filters
- Programmable color matrix pipeline
- Video mixer: 2 video planes as well as 2 graphics planes per video output
Video Output
- Built-in HDMI 2.0a transmitter including both controller as well as PHY with
HDR, CEC as well as HDCP 2,2, 4Kx2K@60 max resolution output
- CVBS 480i/576i touchstone Definition output
- RGB888 TTL interface amongst TCON upwards to 1920x1080 resolution
- Supports all touchstone SD/HD/FHD video output formats: 480i/p, 576i/p, 720p, 1080i/p as well as 4Kx2K
Camera Interface
- ITU 601/656 parallel video input amongst down-scalar
- Supports photographic television receiver camera input every bit YUV422, RGB565,16bit RGB or JPEG
Audio Decoder as well as Input/Output
- Supports MP3, AAC, WMA, RM, FLAC, Ogg as well as programmable amongst 7.1/5.1 down-mixing
- I2S well interface supporting 8-channel (7.1) input as well as output
- Built-in series digital well SPDIF/IEC958 output as well as PCM input/output
- Stereo digital microphone PDM input
- Built-in stereo well DAC
- Supports concurrent dual well stereo channel output amongst combination of analog+PCM or I2S+PCM
Memory as well as Storage Interface
- 16/32-bit SDRAM retentiveness interface running upwards to DDR2400
- Supports upwards to 2GB DDR3/4, DDR3L, LPDDR2/3 amongst dual ranks
- Supports SLC/MLC/TLC NAND Flash amongst 60-bit ECC, compatible to Toshiba toggle agency inwards add-on to ONFI 2.2
- SDSC/SDHC/SDXC bill of fare as well as SDIO interface amongst 1-bit as well as 4-bit information charabanc width supporting spec version 2.x/3.x/4.x DS/HS modes upwards to UHS-I SDR104
- eMMC as well as MMC bill of fare interface amongst 1/4/8-bit information charabanc width fully supporting spec version 5.0 HS400
- Supports series 1, 2 or 4-bit NOR Flash via SPI interface
- Built-in 4k bits One-Time-Programming retentiveness for primal storage
Network
- Integrated IEEE 802.3 10/100/1000M Gigabit Ethernet MAC controller with RGMII interface
- Integrated 10/100M PHY interface
- Supports Energy Efficiency Ethernet (EEE) mode
- Optional 50MHz as well as 125MHz clock output to external Ethernet PHY
- WiFi/IEEE802.11 & Bluetooth supporting via SDIO/USB/UART/PCM
- Network interface optimized for mixed WIFI as well as BT traffic
Digital Television Interface
- Transport current (TS) input interface amongst built-in demux processor for connecting to external digital TV tuner/demodulator as well as 1 output TS interface
- Built-in PWM, I2C as well as SPI interfaces to command tuner as well as demodulator
- Integrated CI+ port as well as ISO 7816 smart bill of fare controller
Integrated I/O Controllers as well as Interfaces
- Triple USB 2.0 high-speed USB I/O, ii USB Hosts as well as 1 USB OTG
- Multiple UART, I2C as well as SPI interface amongst slave select
- Multiple PWMs
- Programmable IR remote input/output controllers
- Built-in 10bit SAR ADC amongst 2 input channels
- Influenza A virus subtype H5N1 educate of General Purpose IOs amongst built-in clit upwards as well as clit down
System, Peripherals as well as Misc. Interfaces
- Integrated full general purpose timers, counters, DMA controllers
- 24 MHz crystal input
- Embedded debug interface using ICE/JTAG
Power Management
- Multiple external ability domains controlled yesteryear PMIC
- Multiple internal ability domains controlled yesteryear software
- Multiple slumber modes for CPU, system, DRAM, etc.
- Multiple internal PLLs for DVFS operation
- Multi-voltage I/O blueprint for 1.8V as well as 3.3V
- Power administration auxiliary processor inwards a dedicated always-on (AO) ability domain that tin forcefulness out communicate amongst an external PMIC
Security
- Trustzone based Trusted Execution Environment (TEE)
- Secured boot, encrypted OTP, encrypted DRAM amongst retentiveness integrity checker, hardware primal ladder as well as internal command buses as well as storage
- Protected retentiveness regions as well as electrical debate information partition
- Hardware based Trusted Video Path (TVP) , video watermarking as well as secured contents (needs SecureOS software)
- Secured IO as well as secured clock
Package
- LFBGA, 15mmx15mm, 0.65 ball pitch, RoHS compliant
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