Highlights
- 2GHz 64-bit quad heart too mortal ARMCortex™ A53 CPU
- 750 MHz+ Penta Core ARM Mali- 450 GPU processor
- HW UHD H.265/VP9 60fps 10-bit video decoder & depression latency 1080p H.264 60fps encoder
- HDR10 too HLG HDR video processing
- TrustZone based safety for DRM video streaming
- WIFI, BT, USB, SD, Ethernet, Analog Audio too TS peripheral ports
- Power administration auxiliary processor
S905X is an advanced application processor designed for OTT/IP Set Top Box(STB) too high-end media box applications. It integrates a powerful CPU/GPU subsystem, a secured 4K video CODEC engine too a best-in-class HDR prototype processing pipeline alongside all major peripherals to cast the ultimate depression mightiness multimedia AP. The primary arrangement CPU is a quad-core ARM Cortex-A53 CPU alongside L1 instruction/data cache for each heart too mortal too a large unified L2 cache to amend arrangement performance. In addition, the Cortex-A53 CPU includes the NEON SIMD co-processor to amend software media processing capability. The quad-core ARM Cortex-A53 CPU tin endure overdriven to 2GHz too has a broad coach connecting to the retentivity sub-system.
The graphic subsystem consists of 2 graphic engines too a flexible video/graphic output pipeline. The v heart too mortal ARM Mali-450 GPU including dual geometry processors (GP) too triple pixel processors (PP).The multi-core GPU processor handles all OpenGL ES 1.1/2.0 too OpenVG graphics programs, spell the 2.5D graphics processor handles additional scaling, alpha, rotation too color infinite conversion operations. Together, the CPU too GPU grip all operating system, networking, user-interface too gaming related tasks. The video output pipeline includes advanced HDR10 too HLG HDR processing, REC709/BT2020 processing, motility adaptive border enhancing deinterlacing, flexible programmable scalar, too many motion painting enhancement filters earlier passing the enhanced prototype to the video output ports.
Amlogic Video Engine (AVE-10) offloads the Cortex-A53 CPUs from all video CODEC processing. It includes dedicated hardware video decoder too encoder. AVE-10 is capable of decoding 4Kx2K resolution video at 60fps alongside consummate Trusted Video Path (TVP) for secure applications too supports total formats including MVC, MPEG-1/2/4, VC-1/WMV, AVS, AVS+, RealVideo, MJPEG streams, H.264, H265-10, VP9-10 too also JPEG pictures alongside no size limitation. The independent encoder is able to encode inwards JPEG or H.264 upward to 1080p at 60fps. S905X integrates all criterion audio/video input/output interfaces including a HDMI2.0a transmitter alongside 3D, HDR, CEC too HDCP 2.2 support, stereo well DAC, a CVBS output, PCM, I2S too SPDIF digital well input/output interfaces, too a stereo PDM digital MIC inputs.
The processor has rich advanced network too peripheral interfaces, including a 10/100M Ethernet MAC alongside FE PHY interface, dual USB 2.0 high-speed ports (one OTG too ane HOST) too multiple SDIO/SD carte du jour controllers, UART, I2C, high-speed SPI too PWMs. Standard evolution surround utilizing GNU/GCC Android tool chain is supported. Please contact your AMLOGIC sales illustration for to a greater extent than information.
CPU Sub-system
- Quad heart too mortal ARM Cortex-A53 CPU upward to 2GHz (DVFS)
- ARMv8-A architecture alongside Neon too Crypto extensions
- 8-stage in-order total dual number pipeline
- Unified arrangement L2 cache
- Advanced TrustZone safety system
- Application based traffic optimization using internal QoS-based switching fabrics
3D Graphics Processing Unit
- Penta-core ARM Mali-450 GPU upward to 750MHz+ (DVFS)
- Dual Geometry Processors too triple Pixel Processors
- Concurrent multi-core processing
- Full scene over-sampled 4X anti-aliasing engine alongside no additional bandwidth usage
- OpenGL ES 1.1/2.0 too OpenVG 1.1 support
2.5D Graphics Processor
- Fast bitblt engine alongside dual inputs too unmarried output
- Programmable raster operations (ROP)
- Programmable polyphase scaling filter
- Supports multiple video formats 4:2:0, 4:2:2 too 4:4:4 too multiple pixel formats (8/16/24/32 bits graphics layer)
- Fast color infinite conversion
- Advanced anti-flickering filter
Crypto Engine
- AES/AES-XTS block aught alongside 128/192/256 bits keys, criterion sixteen bytes block size too streaming ECB, CBC too CTR modes
- DES/TDES block aught alongside ECB too CBC modes supporting 64 bits fundamental for DES too 192 bits fundamental for 3DES
- Built-in hardware True Random Number Generator (TRNG), CRC too SHA-1/SHA-2/HMAC SHA engine
Video/Picture CODEC
- Amlogic Video Engine (AVE) alongside dedicated hardware decoders too encoders
- Supports multiple “secured” video decoding sessions too simultaneous decoding too encoding
Video/Picture Decoding
- VP9 Profile-2 upward to 4Kx2K@60fps
- H.265 HEVC MP-10@L5.1 upward to 4Kx2K@60fps
- H.264 AVC HP@L5.1 upward to 4Kx2K@30fps
- H.264 MVC upward to 1080P@60fps
- MPEG-4 ASP@L5 upward to 1080P@60fps (ISO-14496)
- WMV/VC-1 SP/MP/AP upward to 1080P@60fps
- AVS-P16(AVS+) /AVS-P2 JiZhun Profile upward to 1080P@60fps
- MPEG-2 MP/HL upward to 1080P@60fps (ISO-13818)
- MPEG-1 MP/HL upward to 1080P@60fps (ISO-11172)
- RealVideo 8/9/10 upward to 1080P@60fps
- WebM upward to VGA
- Multiple linguistic communication too multiple format sub-title video support
- MJPEG too JPEG unlimited pixel resolution decoding (ISO/IEC-10918)
- Supports JPEG thumbnail, scaling, rotation too transition effects
- Supports *.mkv,*.wmv,*.mpg, *.mpeg, *.dat, *.avi, *.mov, *.iso,*.mp4, *.rm too *.jpg file formats
Video/Picture Encoding
- Independent JPEG too H.264 encoder alongside configurable performance/bit-rate
- JPEG prototype encoding
- H.264 video encoding upward to 1080P@60fps alongside depression latency
Video Post-Processing Engine
- Supports HDR10 too HLG HDR processing
- Motion adaptive 3D dissonance reduction filter
- Advanced motility adaptive border enhancing de-interlacing engine
- 3:2 pull-down support
- Programmable poly-phase scalar for both horizontal too vertical dimension for zoom too windowing
- Programmable color administration filter (to heighten blue, green, red, confront too other colors)
- Dynamic Non-Linear Luma filter
- Deblocking filters
- Programmable color matrix pipeline
- Video mixer: 2 video planes too 2 graphics planes per video output
Video Output
- Built-in HDMI 2.0a transmitter including both controller too PHY alongside CEC, HDR too HDCP 2.2, 4Kx2K@60 max resolution output
- CVBS 480i/576i criterion Definition output
- Supports all criterion SD/HD/FHD video output formats: 480i/p, 576i/p, 720p, 1080i/p too 4Kx2K
Audio Decoder too Input/Output
- Supports MP3, AAC, WMA, RM, FLAC, Ogg too programmable alongside 7.1/5.1 down-mixing
- I2S well interface supporting 2-channel input too 8-channel (7.1) output
- Built-in series digital well SPDIF/IEC958 output too PCM input/output
- Built-in stereo well DAC
- Stereo digital microphone PDM input
- Supports concurrent dual well stereo channel output alongside combination of analog+PCM or I2S+PCM
Memory too Storage Interface
- 16/32-bit SDRAM retentivity interface running upward to DDR2133
- Supports upward to 2GB DDR3/4, DDR3L, LPDDR2, LPDDR3 alongside dual ranks
- Supports SLC/MLC/TLC NAND Flash alongside 60-bit ECC, compatible to Toshiba toggle manner inwards add-on to ONFI 2.2
- SDSC/SDHC/SDXC carte du jour too SDIO interface alongside 1-bit too 4-bit information coach width supporting spec version 2.x/3.x/4.x DS/HS modes upward to UHS-I SDR104
- eMMC too MMC carte du jour interface alongside 1/4/8-bit information coach width fully supporting spec version 5.0 HS400
- Supports series 1, 2 or 4-bit NOR Flash via SPI interface
- Built-in 4k bits One-Time-Programming retentivity for fundamental storage
Network
- Integrated IEEE 802.3 10/100M Ethernet MAC controller alongside 10/100M PHY interface
- Supports Energy Efficiency Ethernet (EEE) mode
- WiFi/IEEE802.11 & Bluetooth supporting via SDIO/USB/UART/PCM
- Network interface optimized for mixed WIFI too BT traffic
Integrated I/O Controllers too Interfaces
- Dual USB 2.0 high-speed USB I/O, ane USB Host too ane USB OTG
- Multiple UART, I2C too SPI interface alongside slave select
- Multiple PWMs
- Programmable IR remote input/output controllers
- Built-in 10bit SAR ADC alongside 2 input channels
- Influenza A virus subtype H5N1 gear upward of General Purpose IOs alongside built-in line upward too line down
System, Peripherals too Misc. Interfaces
- Integrated full general role timers, counters, DMA controllers
- 24 MHz crystal input
- Embedded debug interface using ICE/JTAG
Power Management
- Multiple external mightiness domains controlled past times PMIC
- Multiple internal mightiness domains controlled past times software
- Multiple slumber modes for CPU, system, DRAM, etc.
- Multiple internal PLLs for DVFS operation
- Multi-voltage I/O blueprint for 1.8V too 3.3V
- Power administration auxiliary processor inwards a dedicated always-on (AO) mightiness domain that tin communicate alongside an external PMIC
Security
- Trustzone based Trusted Execution Environment (TEE)
- Secured boot, encrypted OTP, encrypted DRAM alongside retentivity integrity checker, hardware fundamental ladder too internal command buses too storage
- Protected retentivity regions too electrical debate information partition
- Hardware based Trusted Video Path (TVP) , video watermarking too secured contents (needs SecureOS software)
- Secured IO too secured clock
Package
- LFBGA,13x13mm, 20x20 ball matrix, 0.65 ball pitch, RoHS compliant
- 2GHz 64-bit quad heart too mortal ARMCortex™ A53 CPU
- 750 MHz+ Penta Core ARM Mali- 450 GPU processor
- HW UHD H.265/VP9 60fps 10-bit video decoder & depression latency 1080p H.264 60fps encoder
- HDR10 too HLG HDR video processing
- TrustZone based safety for DRM video streaming
- WIFI, BT, USB, SD, Ethernet, Analog Audio too TS peripheral ports
- Power administration auxiliary processor
S905X is an advanced application processor designed for OTT/IP Set Top Box(STB) too high-end media box applications. It integrates a powerful CPU/GPU subsystem, a secured 4K video CODEC engine too a best-in-class HDR prototype processing pipeline alongside all major peripherals to cast the ultimate depression mightiness multimedia AP. The primary arrangement CPU is a quad-core ARM Cortex-A53 CPU alongside L1 instruction/data cache for each heart too mortal too a large unified L2 cache to amend arrangement performance. In addition, the Cortex-A53 CPU includes the NEON SIMD co-processor to amend software media processing capability. The quad-core ARM Cortex-A53 CPU tin endure overdriven to 2GHz too has a broad coach connecting to the retentivity sub-system.
The graphic subsystem consists of 2 graphic engines too a flexible video/graphic output pipeline. The v heart too mortal ARM Mali-450 GPU including dual geometry processors (GP) too triple pixel processors (PP).The multi-core GPU processor handles all OpenGL ES 1.1/2.0 too OpenVG graphics programs, spell the 2.5D graphics processor handles additional scaling, alpha, rotation too color infinite conversion operations. Together, the CPU too GPU grip all operating system, networking, user-interface too gaming related tasks. The video output pipeline includes advanced HDR10 too HLG HDR processing, REC709/BT2020 processing, motility adaptive border enhancing deinterlacing, flexible programmable scalar, too many motion painting enhancement filters earlier passing the enhanced prototype to the video output ports.
Amlogic Video Engine (AVE-10) offloads the Cortex-A53 CPUs from all video CODEC processing. It includes dedicated hardware video decoder too encoder. AVE-10 is capable of decoding 4Kx2K resolution video at 60fps alongside consummate Trusted Video Path (TVP) for secure applications too supports total formats including MVC, MPEG-1/2/4, VC-1/WMV, AVS, AVS+, RealVideo, MJPEG streams, H.264, H265-10, VP9-10 too also JPEG pictures alongside no size limitation. The independent encoder is able to encode inwards JPEG or H.264 upward to 1080p at 60fps. S905X integrates all criterion audio/video input/output interfaces including a HDMI2.0a transmitter alongside 3D, HDR, CEC too HDCP 2.2 support, stereo well DAC, a CVBS output, PCM, I2S too SPDIF digital well input/output interfaces, too a stereo PDM digital MIC inputs.
The processor has rich advanced network too peripheral interfaces, including a 10/100M Ethernet MAC alongside FE PHY interface, dual USB 2.0 high-speed ports (one OTG too ane HOST) too multiple SDIO/SD carte du jour controllers, UART, I2C, high-speed SPI too PWMs. Standard evolution surround utilizing GNU/GCC Android tool chain is supported. Please contact your AMLOGIC sales illustration for to a greater extent than information.
CPU Sub-system
- Quad heart too mortal ARM Cortex-A53 CPU upward to 2GHz (DVFS)
- ARMv8-A architecture alongside Neon too Crypto extensions
- 8-stage in-order total dual number pipeline
- Unified arrangement L2 cache
- Advanced TrustZone safety system
- Application based traffic optimization using internal QoS-based switching fabrics
3D Graphics Processing Unit
- Penta-core ARM Mali-450 GPU upward to 750MHz+ (DVFS)
- Dual Geometry Processors too triple Pixel Processors
- Concurrent multi-core processing
- Full scene over-sampled 4X anti-aliasing engine alongside no additional bandwidth usage
- OpenGL ES 1.1/2.0 too OpenVG 1.1 support
2.5D Graphics Processor
- Fast bitblt engine alongside dual inputs too unmarried output
- Programmable raster operations (ROP)
- Programmable polyphase scaling filter
- Supports multiple video formats 4:2:0, 4:2:2 too 4:4:4 too multiple pixel formats (8/16/24/32 bits graphics layer)
- Fast color infinite conversion
- Advanced anti-flickering filter
Crypto Engine
- AES/AES-XTS block aught alongside 128/192/256 bits keys, criterion sixteen bytes block size too streaming ECB, CBC too CTR modes
- DES/TDES block aught alongside ECB too CBC modes supporting 64 bits fundamental for DES too 192 bits fundamental for 3DES
- Built-in hardware True Random Number Generator (TRNG), CRC too SHA-1/SHA-2/HMAC SHA engine
Video/Picture CODEC
- Amlogic Video Engine (AVE) alongside dedicated hardware decoders too encoders
- Supports multiple “secured” video decoding sessions too simultaneous decoding too encoding
Video/Picture Decoding
- VP9 Profile-2 upward to 4Kx2K@60fps
- H.265 HEVC MP-10@L5.1 upward to 4Kx2K@60fps
- H.264 AVC HP@L5.1 upward to 4Kx2K@30fps
- H.264 MVC upward to 1080P@60fps
- MPEG-4 ASP@L5 upward to 1080P@60fps (ISO-14496)
- WMV/VC-1 SP/MP/AP upward to 1080P@60fps
- AVS-P16(AVS+) /AVS-P2 JiZhun Profile upward to 1080P@60fps
- MPEG-2 MP/HL upward to 1080P@60fps (ISO-13818)
- MPEG-1 MP/HL upward to 1080P@60fps (ISO-11172)
- RealVideo 8/9/10 upward to 1080P@60fps
- WebM upward to VGA
- Multiple linguistic communication too multiple format sub-title video support
- MJPEG too JPEG unlimited pixel resolution decoding (ISO/IEC-10918)
- Supports JPEG thumbnail, scaling, rotation too transition effects
- Supports *.mkv,*.wmv,*.mpg, *.mpeg, *.dat, *.avi, *.mov, *.iso,*.mp4, *.rm too *.jpg file formats
Video/Picture Encoding
- Independent JPEG too H.264 encoder alongside configurable performance/bit-rate
- JPEG prototype encoding
- H.264 video encoding upward to 1080P@60fps alongside depression latency
Video Post-Processing Engine
- Supports HDR10 too HLG HDR processing
- Motion adaptive 3D dissonance reduction filter
- Advanced motility adaptive border enhancing de-interlacing engine
- 3:2 pull-down support
- Programmable poly-phase scalar for both horizontal too vertical dimension for zoom too windowing
- Programmable color administration filter (to heighten blue, green, red, confront too other colors)
- Dynamic Non-Linear Luma filter
- Deblocking filters
- Programmable color matrix pipeline
- Video mixer: 2 video planes too 2 graphics planes per video output
Video Output
- Built-in HDMI 2.0a transmitter including both controller too PHY alongside CEC, HDR too HDCP 2.2, 4Kx2K@60 max resolution output
- CVBS 480i/576i criterion Definition output
- Supports all criterion SD/HD/FHD video output formats: 480i/p, 576i/p, 720p, 1080i/p too 4Kx2K
Audio Decoder too Input/Output
- Supports MP3, AAC, WMA, RM, FLAC, Ogg too programmable alongside 7.1/5.1 down-mixing
- I2S well interface supporting 2-channel input too 8-channel (7.1) output
- Built-in series digital well SPDIF/IEC958 output too PCM input/output
- Built-in stereo well DAC
- Stereo digital microphone PDM input
- Supports concurrent dual well stereo channel output alongside combination of analog+PCM or I2S+PCM
Memory too Storage Interface
- 16/32-bit SDRAM retentivity interface running upward to DDR2133
- Supports upward to 2GB DDR3/4, DDR3L, LPDDR2, LPDDR3 alongside dual ranks
- Supports SLC/MLC/TLC NAND Flash alongside 60-bit ECC, compatible to Toshiba toggle manner inwards add-on to ONFI 2.2
- SDSC/SDHC/SDXC carte du jour too SDIO interface alongside 1-bit too 4-bit information coach width supporting spec version 2.x/3.x/4.x DS/HS modes upward to UHS-I SDR104
- eMMC too MMC carte du jour interface alongside 1/4/8-bit information coach width fully supporting spec version 5.0 HS400
- Supports series 1, 2 or 4-bit NOR Flash via SPI interface
- Built-in 4k bits One-Time-Programming retentivity for fundamental storage
Network
- Integrated IEEE 802.3 10/100M Ethernet MAC controller alongside 10/100M PHY interface
- Supports Energy Efficiency Ethernet (EEE) mode
- WiFi/IEEE802.11 & Bluetooth supporting via SDIO/USB/UART/PCM
- Network interface optimized for mixed WIFI too BT traffic
Integrated I/O Controllers too Interfaces
- Dual USB 2.0 high-speed USB I/O, ane USB Host too ane USB OTG
- Multiple UART, I2C too SPI interface alongside slave select
- Multiple PWMs
- Programmable IR remote input/output controllers
- Built-in 10bit SAR ADC alongside 2 input channels
- Influenza A virus subtype H5N1 gear upward of General Purpose IOs alongside built-in line upward too line down
System, Peripherals too Misc. Interfaces
- Integrated full general role timers, counters, DMA controllers
- 24 MHz crystal input
- Embedded debug interface using ICE/JTAG
Power Management
- Multiple external mightiness domains controlled past times PMIC
- Multiple internal mightiness domains controlled past times software
- Multiple slumber modes for CPU, system, DRAM, etc.
- Multiple internal PLLs for DVFS operation
- Multi-voltage I/O blueprint for 1.8V too 3.3V
- Power administration auxiliary processor inwards a dedicated always-on (AO) mightiness domain that tin communicate alongside an external PMIC
Security
- Trustzone based Trusted Execution Environment (TEE)
- Secured boot, encrypted OTP, encrypted DRAM alongside retentivity integrity checker, hardware fundamental ladder too internal command buses too storage
- Protected retentivity regions too electrical debate information partition
- Hardware based Trusted Video Path (TVP) , video watermarking too secured contents (needs SecureOS software)
- Secured IO too secured clock
Package
- LFBGA,13x13mm, 20x20 ball matrix, 0.65 ball pitch, RoHS compliant
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